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this document contains information on a new product. spec ifications and information herein are subject to change without notice. ? motorola, inc., 2003. all rights reserved. 1 introduction motorola?s i.mx family of mi croprocessors has demonstrated leadership in the portable handheld market. continuing this legacy, the i.mx series provides a leap in performance with an arm9? microprocessor core and hi ghly integrated system functions. the i.mx products specifically address the requirements of the personal, portable product market by providing intelligent integrated peripherals , an advanced proces sor core, and power management capabilities. the new mc9328mx1 features the advanced and power-efficient arm920t? core that operates at speeds up to 200 mhz. integrated modules, which includ e an lcd controller, static ram, usb support, an a/d converter (with touch panel cont rol), and an mmc/sd host controller, support a suite of peripheral s to enhance any product seeking to provide a rich multimedia experience. in addition, the mc9328mx1 is the first bluetooth? technology-ready applications processor. it is packaged in a 256-pin mold array process- ball grid array (mapbga). figure 1 on page 1 shows the functional block diagram of the mc9328mx1. figure 1. mc9328mx1 functional block diagram watchdog gpio lcd controller jtag/ice cgm timer 1 & 2 pwm standard bootstrap connectivity system control i 2 c mmc/sd spi 1 and uart 1 uart 2 & 3 usb device smartcard i/f bluetooth memory stick? ssi/i 2 s 1 & 2 analog signal human interface video port multimedia multimedia power rtc bus dmac interrupt vmmu cpu complex i cache aipi 1 aipi 2 d cache esram eim & arm9tdmi? system i/o control (dpllx2) controller control (11 chnl) (128k) sdramc accelerator accelerator processor spi 2 host controller mc9328mx1 advance information mc9328mx1/d rev. 3.0, 12/2003 mc9328mx1 (i.mx1) integrated portable system processor contents 1 introduction . . . . . . . . . . . 1 2 signals and connections . . . . . . . . . . 5 3 specifications . . . . . . . . 13 4 pin-out and package information . . . . . . . . . . 91 contact information . . . . . . . . . . . . . .last page
2 mc9328mx1 advance information motorola introduction 1.1 conventions this document uses the following conventions: ? overbar is used to indicate a signal that is active when pulled low: for example, reset . ? logic level one is a voltage that corresponds to boolean true (1) state. ? logic level zero is a voltage that corresponds to boolean false (0) state. ?to set a bit or bits means to establish logic level one. ?to clear a bit or bits means to establish logic level zero. ?a signal is an electronic construct whose state conv eys or changes in stat e convey information. ?a pin is an external physical connec tion. the same pin can be used to connect a number of signals. ? asserted means that a discrete signal is in active logic state. ? active low signals change from logic le vel one to logic level zero. ? active high signals change from logic le vel zero to logic level one. ? negated means that an asserted discret e signal changes logic state. ? active low signals change from logic le vel zero to logic level one. ? active high signals change from logic le vel one to logic level zero. ? lsb means least significant bit or bits , and msb means most significant bit or bits . references to low and high bytes or words are spelled out. ? numbers preceded by a percent sign (%) are bi nary. numbers preceded by a dollar sign ($) or 0x are hexadecimal. 1.2 features to support a wide variety of applications, the mc9328mx1 provides a robust array of features, including the following: ? arm920t microprocessor core ? ahb to ip bus interfaces (aipis) ? external interface module (eim) ? sdram controller (sdramc) ? dpll clock and powe r control module ? three universal asynchronous receiver/transmitters (uart 1 uart 2 and uart 3) ? two serial periphera l interfaces (spi) ? two general-purpose 32-bit counters/timers ? watchdog timer ? real-time clock/sampling timer (rtc) ? lcd controller (lcdc) ? pulse-width modulation (pwm) module ? universal serial bus (usb) device ? multimedia card and secure digita l (mmc/sd) host controller module ? memory stick? host controller (mshc)
introduction motorola mc9328mx1 advance information 3 ? smartcard interf ace module (sim) ? direct memory access controller (dmac) ? two synchronous serial interfaces and inter-ic sound (ssi 1 and ssi 2/i 2 s) module ? inter-ic (i 2 c) bus module ?video port ? general-purpose i/o (gpio) ports ? bootstrap mode ? analog signal processing (asp) module ? bluetooth accelerator (bta) ? multimedia accelerator (mma) ? 256-pin mapbga package 1.3 target applications the mc9328mx1 is targeted for ad vanced information appliances, smart phones, web browsers, digital mp3 audio players, handheld computers based on the popular palm os platform, and messaging applications such as moto rola's wireless cellular pr oducts, including the accompli tm 008 gsm/gprs interactive communicator. 1.4 document revision history the following table provides revision history for th is release. this history includes technical content revisions only and not stylis tic or grammatical changes. table 1. mc9328mx1 data sheet revision history rev. 3.0 revision location revision throughout data sheet changed all references to usb from self-powered only to self-powered and bus-powered. changed all references to dragonball to i.mx. sdram timing in section 3.17, ?sdram memory controller,? on page 71 sdram clock cycle time changed from 11.4 ns to 10.4 ns at 1.8v in all three tables. maximum ratings table 4 on page 13 change to maximu m operation temperature range from 70c to 85c in table and throughout data sheet. 32 k/16 mhz osc signal timing. table 8 on page 15 changed extal32k input jitter (peak to peak) data/ section section 3.8 .2, ?dtack signal timing,? on page 23 updated dtack waveform and timing tables and figures. signals table 3 corrected ms_clki and ms_clko pin descriptions. removed descriptions of svdd and sgnd. section 3.8.3, ?eim external bus timing,? on page 28 clarified signal naming on all waveform diagrams specification updates max temperature ratings and part numbers were updated.
4 mc9328mx1 advance information motorola introduction 1.5 product documentation the following documents are required for a complete description of the mc9328mx1 and are necessary to design properly with the device . especially for thos e not familiar with th e arm920t processor or previous dragonball products , the following documents are helpful wh en used in conjun ction with this manual. arm architecture reference manual (arm ltd., order number arm ddi 0100) arm9dt1 data sheet manual (arm ltd., order number arm ddi 0029) arm technical reference manual (arm ltd., order number arm ddi 0151c) emt9 technical reference manual (arm ltd., order number ddi o157e) mc9328mx1 product brief (order number mc9328mx1p/d) mc9328mx1s reference manual (order number mc9328mx1srm/d) mc68vz328 product brief (order number mc68vz328p/d) mc68vz328 user?s manual (order number mc68vz328um/d) mc68vz328 user?s manual addendum (order number mc68vz328umad/d) mc68sz328 product brief (order number mc68sz328p/d) mc68sz328 user?s manual (order number mc68sz328um/d) the motorola manuals are ava ilable on the motorola semic onductors web site at http:// www.motorola.com/semiconductors. these documents may be download ed directly from the motorola web site, or printed versions may be ordere d. the arm documentation is available from http://www.arm.com. 1.6 ordering information table 2 provides ordering information for the 256-le ad mold array process ball grid array (mapbga) package. table 2. mc9328mx1 ordering information package type frequency temperature solderball type order number 256-lead mapbga 200 mhz 0c to 70c standard mc9328mx1vh20(r2) 256-lead mapbga 200 mhz 0c to 70c pb-free mc9328mx1vm20(r2) 256-lead mapbga 200 mhz -30c to 70c standard mc9328mx1dvh20(r2) 256-lead mapbga 200 mhz -30c to 70c pb-free mc9328mx1dvm20(r2) 256-lead mapbga 150 mhz -40c to 85c standard mc9328mx1cvh15(r2) 256-lead mapbga 150 mhz -40c to 85c pb-free mc9328mx1cvm15(r2)
signals and connections motorola mc9328mx1 advance information 5 2 signals and connections table 3 identifies and describes the mc9328mx1 signal s that are assigned to package pins. the signals are grouped by the internal modu le that they are connected to. table 3. signal names and descriptions signal name function/notes external bus/chip select (eim) a [24:0] address bus signals d [31:0] data bus signals eb0 msb byte strobe?active low external enab le byte signal that controls d [31:24] eb1 byte strobe?active low external enable byte signal that controls d [23:16] eb2 byte strobe?active low external enable byte signal that controls d [15:8] eb3 lsb byte strobe?active low external enabl e byte signal that controls d [7:0] oe memory output enable?active low ou tput enables external data bus cs [5:0] chip select?the chip select signals cs [3:2] are multiplexed with csd [1:0] and are selected by the function multiplexing control register (fmcr). by default csd [1:0] is selected. ecb active low input signal sent by flash device to the eim whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. lba active low signal sent by flash device causing th e external burst device to latch the starting burst address. bclk clock signal sent to external synchronous memories (such as burst flash) during burst mode. rw rw signal?indicates whether external access is a read (high) or write (low) cycle. used as a we input signal by external dram. bootstrap boot [3:0] system boot mode select?the operational system boot mode of the mc9328mx1 upon system reset is determined by the settings of these pins. sdram controller sdba [4:0] sdram/syncflash non-interleave mode bank address multiplexed with address signals a [15:11]. these signals are logically equivalent to core address p_addr [25:21] in sdram/ syncflash cycles. sdiba [3:0] sdram/syncflash interleave addressing mode bank address multiplexed with address signals a [19:16]. these signals are logically e quivalent to core address p_addr [12:9] in sdram/syncflash cycles. ma [11:10] sdram address signals
6 mc9328mx1 advance information motorola signals and connections ma [9:0] sdram address signals which are multiplex with address signals a [10:1]. ma [9:0] are selected on sdram/syncflash cycles. dqm [3:0] sdram data enable csd0 sdram/syncflash chip select signal which is multiplexed with the cs2 signal. these two signals are selectable by progra mming the system control register. csd1 sdram/syncflash chip select signal which is multiplex with cs3 signal. these two signals are selectable by programming the system control regist er. by default, csd1 is selected, so it can be used as syncflash b oot chip select by properly configuring boot [3:0] input pins. ras sdram/syncflash row address select signal cas sdram/syncflash column address select signal sdwe sdram/syncflash write enable signal sdcke0 sdram/syncflash clock enable 0 sdcke1 sdram/syncflash clock enable 1 sdclk sdram/syncflash clock reset_sf syncflash reset clocks and resets extal16m crystal input (4 mhz to 16 mhz), or a 16 mhz oscillator input when internal oscillator circuit is shut down. xtal16m crystal output extal32k 32 khz crystal input xtal32k 32 khz crystal output clko clock out signal selected from internal clock signals. please refer to clock controller for internal clock selection. reset_in master reset?external active low schmitt trigger input signal. when this signal goes active, all modules (except the reset module and the clock control module) are reset. reset_out reset out?internal active low output signal from the watchdog timer module and is asserted from the following sources: power-on reset, exte rnal reset (reset_in ), and watchdog time-out. por power on reset?internal active high schmit t trigger input signal. the por signal is normally generated by an external rc circuit designed to detect a power-up event. jtag trst test reset pin?external active low signal used to asynchronously initialize the jtag controller. tdo serial output for test instructions and data. changes on the falling edge of tck. table 3. signal names and descriptions (continued) signal name function/notes
signals and connections motorola mc9328mx1 advance information 7 tdi serial input for test instructions and data. sampled on the rising edge of tck. tck test clock to synchronize test logic and cont rol register access through the jtag port. tms test mode select to sequence the jtag test controller?s state mach ine. sampled on the rising edge of tck. system big_endian big_endian?this signal determines the memory endian configuration. big_endian is a static pin to inner module. if the pin is dr iven logic-high the memory system is configured into big endian. if it is driven logic-low the memory system is configur ed into litt le endian. the pin is not supposed to be changed on the fly. etm etmtracesync etm sync signal which is multiplexed with a24. etmtracesync is selected in etm mode. etmtraceclk etm clock signal which is multiplexed with a23. etmtraceclk is selected in etm mode. etmpipestat [2:0] etm status signals which are mu ltiplex with a [22:20]. etmp ipestat [2:0] are selected in etm mode. etmtracepkt [7:0] etm packet signals which are multiplex with ecb , lba , bclk , pa17, a [19:16]. etmtracepkt [7:0] are selected in etm mode. cmos sensor interface csi_d [7:0] sensor port data csi_mclk sensor port master clock csi_vsync sensor port vertical sync csi_hsync sensor port horizontal sync csi_pixclk sensor port data latch clock lcd controller ld [15:0] lcd data bus?all lcd signals are driven low after reset and when lcd is off. flm/vsync frame sync or vsync?this signal also serves as the clock signal output for gate. driver (dedicated signal sps for sharp panel hr-tft). lp/hsync line pulse or h sync lsclk shift clock acd/oe alternate crystal direction/output enable contrast this signal is used to control the lcd bias voltage as contrast control. spl_spr program horizontal scan direction (sharp panel dedicated signal). table 3. signal names and descriptions (continued) signal name function/notes
8 mc9328mx1 advance information motorola signals and connections ps control signal output for source dr iver (sharp panel dedicated signal). cls start signal output for gate driver. this signal is invert version of ps (sharp panel dedicated signal). rev signal for common electrode driving signal preparation (sharp panel dedicated signal). sim sim_clk sim clock sim_rst sim reset sim_rx receive data sim_tx transmit data sim_pd presence detect schmitt trigger input sim_sven sim vdd enable spi spi1_mosi master out/slave in spi1_miso slave in/master out spi1_ss slave select (selectable polarity) spi1_sclk serial clock spi1_spi_rdy serial data ready spi2_txd spi2 master txdata output?this signal is mu ltiplexed with a gpi/o pin however it does show up as a primary or alternative signal in the signal multiplex scheme table. refer to chapter 16, ?serial peripheral interface m odules (spi 1 and spi 2),? and chapter 29, ?gpio module and i/o multiplexer (iomux),? for information on how to bring this signal to the assigned pin. spi2_rxd spi2 master rxdata input?this signal is multiplexed with a gpi/o pin however it does show up as a primary or alternative signal in the signal multiplex scheme table. refer to chapter 16, ?serial peripheral interface m odules (spi 1 and spi 2),? and chapter 29, ?gpio module and i/o multiplexer (iomux),? for information on how to bring this signal to the assigned pin. spi2_ss spi2 slave select?this signal is multiplexed with a gpi/o pin, however it does show up as a primary or alternative signal in the signa l multiplex scheme table. refer to chapter 16, ?serial peripheral interface modules (spi 1 and spi 2),? and chapter 29, ?gpio module and i/o multiplexer (iomux),? for information on how to bring this signal to the assigned pin. spi2_sclk spi2 serial clock?this signal is multiplexed with a gpi/o pin however it does show up as a primary or alternative signal in the signal multiplex scheme table. refer to chapter 16, ?serial peripheral interface modules (spi 1 and spi 2),? and chapter 29, ?gpio module and i/o multiplexer (iomux),? for information on how to bring this signal to the assigned pin. table 3. signal names and descriptions (continued) signal name function/notes
signals and connections motorola mc9328mx1 advance information 9 general purpose timers tin timer input capture or timer input clock?the sign al on this input is a pplied to both timers simultaneously. tmr2out timer 2 output usb device usbd_vmo usb minus output usbd_vpo usb plus output usbd_vm usb minus input usbd_vp usb plus input usbd_suspnd usb suspend output usbd_rcv usb rxd usbd_oe usb oe usbd_afe usb analog front end enable secure digital interface sd_cmd sd command?if the system designer does not wa nt to make use of the internal pull-up, via the pull-up enable register, a 4.7k?69k external pull up resistor must be added. sd_clk mmc output clock sd_dat [3:0] data?if the system designer does not want to make use of the internal pull-up, via the pull-up enable register, a 50 k?69k external pull up resistor must be added. memory stick interface ms_bs memory stick bus state (output)?serial bus control signal ms_sdio memory stick serial data (input/output) ms_sclko memory stick seri al clock (output) ? serial protocol clock output ms_sclki memory stick exte rnal clock (input) ? test clock input pin for sclk divider. this pin is only for test purposes, not for use in application mode. ms_pi0 general purpose input0?can be used for me mory stick insertion/extraction detect ms_pi1 general purpose input1?can be used for me mory stick insertion/extraction detect uarts ? irda/auto-bauding uart1_rxd receive data uart1_txd transmit data table 3. signal names and descriptions (continued) signal name function/notes
10 mc9328mx1 advance information motorola signals and connections uart1_rts request to send uart1_cts clear to send uart2_rxd receive data uart2_txd transmit data uart2_rts request to send uart2_cts clear to send uart2_dsr data set ready uart2_ri ring indicator uart2_dcd data carrier detect uart2_dtr data terminal ready uart3_rxd receive data uart3_txd transmit data uart3_rts request to send uart3_cts clear to send uart3_dsr data set ready uart3_ri ring indicator uart3_dcd data carrier detect uart3_dtr data terminal ready serial audio ports ? ssi (configurable to i2s protocol) ssi1_txdat txd ssi1_rxdat rxd ssi1_txclk transmit serial clock ssi1_rxclk receive serial clock ssi1_txfs transmit frame sync ssi1_rxfs receive frame sync ssi2_txdat txd ssi2_rxdat rxd ssi2_txclk transmit serial clock ssi2_rxclk receive serial clock table 3. signal names and descriptions (continued) signal name function/notes
signals and connections motorola mc9328mx1 advance information 11 ssi2_txfs transmit frame sync ssi2_rxfs receive frame sync i 2 c i2c_scl i 2 c clock i2c_sda i 2 c data pwm pwmo pwm output asp uin positive u analog input (for lo w voltage, temperature measurement) uip negative u analog input (for low vo ltage, temperature measurement) px1 positive pen-x analog input py1 positive pen-y analog input px2 negative pen-x analog input py2 negative pen-y analog input r1a positive resistance input (a) r1b positive resistance input (b) r2a negative resistance input (a) r2b negative resistance input (b) rvp positive reference for pen adc rvm negative reference for pen adc avdd analog power supply agnd analog ground bluetooth bt1 i/o clock signal bt2 output bt3 input bt4 input bt5 output table 3. signal names and descriptions (continued) signal name function/notes
12 mc9328mx1 advance information motorola signals and connections bt6 output bt7 output bt8 output bt9 output bt10 output bt11 output bt12 output bt13 output tristate sets all i/o pins to tristate; can be used for flash loading and is pulled low for normal operations. btrf vdd power supply from external bt rfic btrf gnd ground from external bt rfic noisy supply pins nvdd noisy supply for the i/o pins nvss noisy ground for the i/o pins supply pins ? analog modules avdd supply for analog blocks avss quiet gnd for analog blocks internal power supply qvdd power supply pins for silicon internal circuitry qvss gnd pins for silicon internal circuitry table 3. signal names and descriptions (continued) signal name function/notes
specifications motorola mc9328mx1 advance information 13 3 specifications this section contains the electrical specifications and timing diagrams for the mc9328mx1 processor. 3.1 maximum ratings table 4 provides information on maximum ratings. 3.2 recommended operating range table 5 provides the recommended operating ranges for the supply voltages. the mc9328mx1 processor has multiple pairs of vdd and vss power supply and return pins. qvdd and qvss pins are used for internal logic. all other vdd and vss pins are for the i/o pads voltage supply, and each pair of vdd and vss provides power to the enclosed i/o pads. this desi gn allows different peripher al supply voltage levels in a system. because avdd pins are suppl y voltages to the analog pads, it is recomme nded to isolate and noise-filter the avdd pins from other vdd pins. btrfvdd is the supply voltage for th e bluetooth interface signals. it is quite sensitive to the data transmit/receive accur acy. please refer to bluetooth rf spec for special handling. if bluetooth is not used in the system, these bluetooth pins can be used as general purpose i/o pins and btrfvdd can be used as other nvdd pins. table 4. maximum ratings rating symbol minimum maximum unit supply voltage v dd -0.3 3.3 v maximum operating temperature range mc9328mx1vh20/mc9328mx1vm20 t a 070c maximum operating temperature range mc9328mx1dvh20/mc9328mx1dvm20 t a -30 70 c maximum operating temperature range mc9328mx1cvh15/mc9328mx1cvm15 t a -40 85 c esd at human body model (hbm) vesd_hbm ? 2000 v esd at machine model (mm) vesd_mm ? 100 v latch-up current ilatchup ? 200 ma storage temperature test -55 150 c power consumption pmax 800 1 1. a typical application with 30 pads simultaneously s witching assumes the gpio toggling and instruction fetches from the arm core-that is, 7x gp io, 15x data bus, and 8x address bus. 1300 2 2. a worst-case application with 70 pads simultaneously switching assumes the gpio toggling and instruction fetches from the arm core-that is, 32x gpio, 30x data bus, 8x address bus. these calculations are based on the core running its heav iest os application at 200mhz, and where the whole image is running out of sdram. qvdd at 2.0v, nvdd and avdd at 3.3v, therefore, 180ma is the worst measurement recorded in the factory environment, max 5ma is consumed for osc pads, with each toggle gpio consuming 4ma. mw
14 mc9328mx1 advance information motorola specifications for more information about i/o pads groupi ng per vdd, please refer to table 3 on page 5. 3.3 dc electrical characteristics table 6 contains both maximum and minimum dc characteristics of the mc9328mx1. table 5. recommended operating range rating symbol mini mum maximum unit i/o supply voltage, mshc, spi, bta, usbd, lcd and csi are only 3v interface nvdd 2.70 3.30 v i/o supply voltage nvdd 1.70 3.30 v internal supply voltage (core = 150 mhz) qvdd 1.70 1.90 v internal supply voltage (core = 200 mhz) qvdd 1.80 2.00 v analog supply voltage avdd 1.70 3.30 v bluetooth i/o voltage (bluetooth) btrfvdd 1 1.70 3.10 v bluetooth i/o voltage (non bl uetooth applications) btrfvdd 2 1.70 3.30 v table 6. maximum and minimum dc characteristics number or symbol parameter minimum typical maximum unit iop full running operating current at 1.8v for qvdd, 3.3v for nvdd/avdd (core = 96 mhz, system = 96 mhz, mpeg4 decoding playback from external memory card to bo th external ssi audio decoder and tft display panel, and os with mmu enabled memory system is running on external sdram) please refer to application note: an2537, power performance of mc9328mx1. ? qvdd at 1.8v = 120ma; nvdd+avdd at 3.0v = 30ma ?ma sidd 1 standby current (qvdd = 1.8v, temp = 25 c) ?25 ? a sidd 2 standby current (qvdd = 1.8v, temp = 55 c) ?45 ? a sidd 3 standby current (qvdd = 2.0v, temp = 25 c) ?35 ? a sidd 4 standby current (qvdd = 2.0v, temp = 55 c) ?60 ? a v ih input high voltage 0.7v dd ?vdd+0.2v v il input low voltage ? ? 0.4 v
specifications motorola mc9328mx1 advance information 15 3.4 ac electrical characteristics the ac characteristics consist of output delays, input setup and hold times, and signal skew times. all signals are specified relative to an appropriate edge of other signals. all timing specifications are specified at a system operating frequency from 0 mhz to 96 mhz (core operating frequency 150 mhz) with an operating supply voltage from v dd min to v dd max under an operating temperature from t l to t h . all timing is measured at 30 pf loading. v oh output high voltage (i oh =2.0ma) 0.7v dd ?vddv v ol output low voltage (i ol =-2.5ma) ? ? 0.4 v v it+ positive input threshold voltage, v i =v ih ? ? 1.126 v v it- negative input threshold voltage, v i =v il 0.640 ? ? v v hys hysteresis (v it+ ? v it-) =v ih ?0.3 ?? i il input low leakage current (v in = gnd, no pull-up or pull-down) ??1 a i ih input high leakage current (v in =v dd , no pull-up or pull-down) ??1 a i oh output high current (v oh =0.8v dd , v dd =1.8v) ??4.0ma i ol output low current (v ol =0.4v, v dd =1.8v) ? 4.0 ??ma i oz output leakage current (v out =v dd , output is tri-stated) ??5 a c i input capacitance ? ? 5 pf c o output capacitance ? ? 5 pf table 7. tri-state signal timing pin parameter minimum maximum unit tristate time from tristate acti vate until i/o becomes hi-z ? 20.8 ns table 8. 32k/16m oscillator signal timing parameter minimum rms maximum unit extal32k input jitter (peak to peak) for both system pll and mcupll ? 5 20 ns table 6. maximum and minimum dc characteristics (continued) number or symbol parameter minimum typical maximum unit
16 mc9328mx1 advance information motorola specifications extal32k input jitter (peak to peak) for mcupll only ? 5 100 ns extal32k startup time 800 ? ? ms extal16m input jitter (peak to peak) ? tbd tbd ? extal16m startup time tbd ? ? ? table 9. clko rise/fall time (at 30pf loaded) best case typical worst case units rise time 0.80 1.00 1.40 ns fall time 0.74 1.08 1.67 ns table 8. 32k/16m oscillator signal timing (continued) parameter minimum rms maximum unit
specifications motorola mc9328mx1 advance information 17 3.5 embedded trace macrocell all registers in the etm9 are prog rammed through a jtag interface. the interface is an extension of the arm920t processor?s tap controller, and is assigned scan chain 6. th e scan chain consists of a 40-bit shift register comprised of the following: ? 32-bit data field ? 7-bit address field ? a read/write bit the data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. a register is read by scanning its address into the a ddress field and a 0 into the read/write bit. the 32-bit data field is ignored. a read or a write takes place when the tap controller enters the update-dr state. the timing diagram for the etm9 is shown in figure 2. see table 10 on page 17 for the etm9 timing parameters used in figure 2. figure 2. trace port timing diagram table 10. trace port timi ng diagram parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimummaximumminimummaximum 1 clk frequency 0 85 0 100 mhz 2a clock high time 1.3 ? 2 ? ns 2b clock low time 3 ? 2 ? ns 3a clock rise time ? 4 ? 3 ns 3b clock fall time ? 3 ? 3 ns 4a output hold time 2.28 ? 2 ? ns 4b output setup time 3.42 ? 3 ? ns traceclk 4b 4a 3b 2a 1 output trace port 3a valid data valid data 2b traceclk (half-rate clocking mode)
18 mc9328mx1 advance information motorola specifications 3.6 dpll timing specifications parameters of the dpll are given in table 11. in this table, t ref is a reference clock period after the pre-divider and t dck is the output double clock period. table 11. dpll specifications parameter test conditions minimum typical maximum unit reference clock freq range vcc = 1.8v 5 ? 100 mhz pre-divider output clock freq range vcc = 1.8v 5 ? 30 mhz double clock freq range vcc = 1.8v 80 ? 220 mhz pre-divider factor (pd) ? 1 ? 16 ? total multiplication factor (mf) includes both integer and fractional parts 5?15? mf integer part ?5?15? mf numerator should be less than the denominator 0 ? 1022 ? mf denominator ? 1 ? 1023 ? pre-multiplier lock-in time ? ? ? 312.5 sec freq lock-in time after full reset fol mode for non-integer mf (does not include pre-must lock-in time) 250 280 (56 s) 300 t ref freq lock-in time after partial reset fol mode for non-integer mf (does not include pre-multi lock-in time) 220 250 (~50 s) 270 t ref phase lock-in time after full reset fpl mode and integer mf (does not include pre-multi lock-in time) 300 350 (70 s) 400 t ref phase lock-in time after partial reset fpl mode and integer mf (does not include pre-multi lock-in time) 270 320 (64 s) 370 t ref freq jitter (p-p) ? ? 0.005 (0.01%) 0.01 2t dck phase jitter (p-p) integer mf, fpl mode, vcc=1.8v ? 1.0 (10%) 1.5 ns power supply voltage ? 1.7 ? 2.5 v power dissipation fol mode, integer mf, f dck = 200 mhz, vcc = 1.8v ?? 4mw
specifications motorola mc9328mx1 advance information 19 3.7 reset module the timing relationships of the rese t module with the por and reset_in are shown in figure 3 and figure 4. be aware that nvdd must ramp up to at least 1.8v before qvdd is powered up to prevent forward biasing. figure 3. timing relationship with por figure 4. timing relationship with reset_in por reset_por reset_dram hreset reset_out clk32 hclk 90% avdd 10% avdd could be adjust due to 32khz crystal start-up time 1 2 3 4 exact 300ms 7 cycles @ clk32 14 cycles @ clk32 14 cycles @ clk32 reset_in clk32 hclk 5 4 hreset reset_out 6
20 mc9328mx1 advance information motorola specifications 1 timing waveforms shown are dependent on crystal start- up time. if a stable clock source is used instead of a crystal, the width of the por should be ignored in calculating timing for the startup process. table 12. reset module timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit min max min max 1 width of input power_on_reset 1 800 ? 800 ? ns 2 width of internal power_on_reset (9600 *clk32 at 32 khz) 300 300 300 300 ms 3 7k to 32k-cycle stretcher for sdram reset 7 7 7 7 cycles of clk32 4 14k to 32k-cycle stretcher for internal system reset hresert and output reset at pin reset_out 14 14 14 14 cycles of clk32 5 width of external hard-reset reset_in 4 ? 4 ? cycles of clk32 6 4k to 32k-cycle qualifier 4 4 4 4 cycles of clk32
specifications motorola mc9328mx1 advance information 21 3.8 external interface module the external interface module (e im) handles the interface to devi ces external to the mc9328mx1, including generation of chip-selects for external peripherals and memo ry. the timing diagram for the eim is shown in figure 5, and table 13 defines the parameters of signals. figure 5. eim bus timing diagram table 13. eim bus timing parameter table ref no. parameter 1.8 0.10v 3.0 0.3v unit min typical max min typical max 1a clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns 1b clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns 1a 1b 2a 2b 3b 3a 4a 4b 4c 4d 5a 5b 5c 5d 6a 6a 6b 6c 7a 7b 7c 8a 8b 9b 9c 9a 9a 7d (hclk) bus clock address chip-select read (write ) oe (rising edge) lba (negated rising edge) oe (falling edge) burst clock (rising edge) lba (negated falling edge) eb (falling edge) eb (rising edge) burst clock (falling edge) read data write data (negated falling) write data (negated rising) dtack_b 10a 10a
22 mc9328mx1 advance information motorola specifications 2a clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns 2b clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns 3a clock fall to read (write ) valid 1.35 2.79 6.52 1.3 2.7 6.3 ns 3b clock fall to read (write ) invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns 4a clock 1 rise to output enable valid 2.32 2.62 6.85 2.3 2.6 6.8 ns 4b clock 1 rise to output enable invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns 4c clock 1 fall to output enable valid 2.38 2.69 7.04 2.3 2.6 6.8 ns 4d clock 1 fall to output enable invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns 5a clock 1 rise to enable bytes valid 1.91 2.52 5.54 1.9 2.5 5.5 ns 5b clock 1 rise to enable bytes invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns 5c clock 1 fall to enable bytes va lid 1.97 2.59 5.69 1.9 2.5 5.5 ns 5d clock 1 fall to enable bytes in valid 1.76 2.48 5.38 1.7 2.4 5.2 ns 6a clock 1 fall to load burst address valid 2.07 2.79 6.73 2.0 2.7 6.5 ns 6b clock 1 fall to load burst address invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns 6c clock 1 rise to load burst address invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns 7a clock 1 rise to burst clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns 7b clock 1 rise to burst clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns 7c clock 1 fall to burst clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns 7d clock 1 fall to burst clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns 8a read data setup time 5.54 ? ? 5.5 ? ? ns 8b read data hold time 0 ? ? 0 ? ? ns 9a clock 1 rise to write data valid 1.81 2.72 6.85 1.8 2.7 6.8 ns 9b clock 1 fall to write data inva lid 1.45 2.48 5.69 1.4 2.4 5.5 ns 9c clock 1 rise to write data invalid 1.63 ? ? 1.62 ? ? ns 10a dtack setup time 2.52 ? ? 2.5 ? ? ns 1. clock refers to the system clock signal , hclk, generated from the system dpll table 13. eim bus timing parameter table (continued) ref no. parameter 1.8 0.10v 3.0 0.3v unit min typical max min typical max
specifications motorola mc9328mx1 advance information 23 3.8.1 dtack signal description the dtack signal is the external inpu t data acknowledge signal. when using the external dtack signal as a data acknowledge signal, the bus time-out moni tor generates a bus error when a bus cycle is not terminated by the external dtack signal after 1022 hclk counts have elapsed only cs5 group supports dtack signal function when using the external dtack signal for data acknowledgement. 3.8.2 dtack signal timing figure 6 through figure 9 show the access cycle timing u sed by chip-select 5. the signal values and units of measure for this figure ar e found in the associated tables. 3.8.2.1 dtack rea d cycle without dma figure 6. dtack read cycle without dma table 14. parameters fo r read cycle, wsc = 111111, dtack_sel=0, hkcl=96mhz number characteristic (3.0 0.3) v unit minimum maximum 1oe and eb assertion time see note 2 ? ns 2cs5 pulse width 3t ? ns 3oe negated to address inactive 46.44 ? ns 4 dtack asserted after cs5 asserted ? 1019t ns 5 dtack asserted to oe negated 3t+2.2 4t+6.86 ns 6 data hold timing after oe negated 0 ? ns dtack address eb cs5 oe databus programmable min 0ns (1) (5) (6) (3) (2) (4) (7) (input to mx1) (8) (9) (10)
24 mc9328mx1 advance information motorola specifications 3.8.2.2 dtack read cycle dma enabled figure 7. dtack r ead cycle dma enabled 7 data ready after dtack asserted 0 t ns 8 oe negated to cs negated 0.5t+0.24 0.5t+0.67 ns 9 oe negated after eb negated 0.5 1.5 ns 10 dtack pulse width 1t 3t ns note : 0. dtack assert means dtack become low level. 1. t is the system clock per iod. (for 96mhz system clock) 2. oe and eb assertion time is programmable by oea bit in cs5l register. eb assertion in read cycle will occur only when ebc bit in cs5l register is clear. 3. address becomes valid and cs asserts at the start of read access cycle. 4. the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. table 15. parameters for read cycle wsc = 111111, dtack_sel=0, hclk=96mhz number characteristic (3.0 0.3) v unit minimum maximum 1oe and eb assertion time see note 2 ? ns table 14. parameters for read cycle, wsc = 111111, dt ack_sel=0, hkcl=96mhz (continued) number characteristic (3.0 0.3) v unit minimum maximum rw dtack address eb cs5 oe (logic high) databus programmable min 0ns (1) (6) (7) (3) (4) (2) (5) (8) (input to mx1) (9) (10) (11)
specifications motorola mc9328mx1 advance information 25 2cs pulse width 3t ? ns 3oe negated before cs5 is negated 0.5t+0.24 0.5t+0.67 ns 4 address inactive before cs negated ? 0.93 ns 5 dtack asserted after cs5 asserted ? 1019t ns 6 dtack asserted to oe negated 3t+2.2 4t+6.86 ns 7 data hold timing after oe negated 0 ? ns 8 data ready after dtack is asserted ? t ns 9cs deactive to next cs active t ? ns 10 oe negate after eb negate 0.5 1.5 ns 11 dtack pulse width 1t 3t ns note : 0. dtack assert mean dtack become low. 1. t is the system clock period. (for 96mhz system clock) 2. oe and eb assertion time is programmable by oea bit in cs5l register. eb assertion in read cycle will occur only when ebc bit in cs5l register is clear. 3. address becomes valid and cs asserts at the start of read access cycle. 4. the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. table 15. parameters for read cycle wsc = 111111, dtack_sel=0, hclk=96mhz (continued) number characteristic (3.0 0.3) v unit minimum maximum
26 mc9328mx1 advance information motorola specifications 3.8.2.3 dtack writ e cycle without dma figure 8. dtack write cycle without dma table 16. parameters for write cycle wsc = 111111, dtack_sel=0, hkcl=96mhz number characteristic (3.0 0.3) v unit minimum maximum 1cs5 assertion time see note 2. ? ns 2eb assertion time see note 2 ? ns 3cs5 pulse width 3t ? ns 4rw negated before cs5 is negated 1.5t+0.58 1.5t+1.58 ns 5rw negated to address inactive 57.31 ? ns 6 dtack asserted after cs5 asserted ? 1019t ns 7 dtack asserted to rw negated 2t+1.8 3t+5.26 ns 8 data hold timing after rw negated 1.5t-0.59 ? ns 9 data ready after cs5 is asserted ? t ns 10 eb negated before cs5 is negated 0.5t+0.74 0.5t+2.17 ns 11 dtack pulse width 1t 3t ns note : 0. dtack assert mean dtack become low. 1. t is the system clock period. (for 96mhz system clock) 2. cs5 assertion can be controlled by csa bits. eb assertion can also be programmed by wea bits in the cs5l register. 3. address becomes valid and rw asserts at the start of write access cycle. 4. the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. oe dtack address eb cs5 rw (logic high) databus programmable min 0ns programmable min 0ns (1) (2) (7) (8) (4) (5) (3) (6) (9) (output from mx1) (10) (11)
specifications motorola mc9328mx1 advance information 27 3.8.2.4 dtack writ e cycle dma enabled figure 9. dtack write cycle dma enabled table 17. wsc = parameters for write cycle 111111, dtack_sel=0, hclk=96mhz number characteristic (3.0 0.3) v unit minimum maximum 1 cs5 assertion time see note 2 ? ns 2eb assertion time see note 2 ? ns 3cs5 pulse width 3t ? ns 4rw negated before cs5 is negated 1.5t+0.58 1.5t+1.58 ns 5 address inactive before cs negated ? 0.93 ns 6 dtack asserted after cs5 asserted ? 1019t ns 7 dtack asserted to rw negated 2t+1.8 3t+5.26 ns 8 data hold timing after rw negated 1.5t-0.59 ? ns 9 data ready after cs5 is asserted ? t ns 10 cs deactive to next cs active t ? ns 11 eb negate to cs negate 0.5t+0.74 0.5t+2.17 ns 12 dtack pulse width 1t 3t ns note : 0. dtack assert mean dtack become low. 1. t is the system clock peri od. (for 96mhz system clock) 2. cs5 assertion can be controlled by csa bits. eb assertion also can be programmed by wea bits in the cs5l register. 3. address becomes valid and rw asserts at the start of write access cycle. 4.the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. oe dtack address eb cs5 rw (logic high) databus programmable min 0ns programmable min 0ns (1) (2) (7) (8) (4) (5) (3) (6) (9) (output from mx1) (10) (11) (12)
28 mc9328mx1 advance information motorola specifications 3.8.3 eim external bus timing the following timing diagrams show the timi ng of accesses to memory or a peripheral. figure 10. wsc = 1, a.half/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hrdata weim_hready bclk addr cs2 r/w lba oe ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) data read seq/nonseq v1 last valid data last valid address read v1 v1 v1 internal signals - shown only for illustrative purposes note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
specifications motorola mc9328mx1 advance information 29 figure 11. wsc = 1, wea = 1, wen = 1, a.half/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready hwdata weim_hready write nonseq v1 last valid data last valid address weim_hrdata write data (v1) unknown last valid data v1 write last valid data write data (v1) bclk addr cs0 r/w lba oe eb data internal signals - shown only for illustrative purposes
30 mc9328mx1 advance information motorola specifications figure 12. wsc = 1, oea = 1, a.word/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hready bclk addr cs 0 r/w lba oe data weim_hrdata read nonseq v1 last valid data address v1 v1 word read address v1 + 2 last valid addr 1/2 half word 2/2 half word internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
specifications motorola mc9328mx1 advance information 31 figure 13. wsc = 1, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hready weim_hrdata hwdata write nonseq v1 last valid data address v1 write data (v1 word) write address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data bclk addr cs0 r/w lba oe eb data internal signals - shown only for illustrative purposes
32 mc9328mx1 advance information motorola specifications figure 14. wsc = 3, oea = 2, a.word/e.half hclk hsel_weim_cs[3] htrans hwrite haddr hready weim_hready bclk addr cs [3] r/w ba oe data weim_hrdata read nonseq v1 last valid data address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word read internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
specifications motorola mc9328mx1 advance information 33 figure 15. wsc = 3, wea = 1, wen = 3, a.word/e.half hclk hsel_weim_cs[3] htrans hwrite haddr hready weim_hready bclk addr cs 3 r/w lba oe data weim_hrdata eb hwdata write nonseq v1 last valid data address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data internal signals - shown only for illustrative purposes
34 mc9328mx1 advance information motorola specifications figure 16. wsc = 3, oea = 4, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs 2 r/w lba oe weim_data_in weim_hrdata read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register internal signals - shown only for illustrative purposes
specifications motorola mc9328mx1 advance information 35 figure 17. wsc = 3, wea = 2, wen = 3, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs 2 r/w lba oe data hwdata eb weim_hrdata write nonseq v1 address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data last valid data internal signals - shown only for illustrative purposes
36 mc9328mx1 advance information motorola specifications figure 18. wsc = 3, oen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs 2 r/w lba oe data weim_hrdata read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
specifications motorola mc9328mx1 advance information 37 figure 19. wsc = 3, oea = 2, oen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs2 r/w lba oe data weim_hrdata read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
38 mc9328mx1 advance information motorola specifications figure 20. wsc = 2, wws = 1, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs2 r/w lba oe weim_hrdata eb data hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) write last valid data internal signals - shown only for illustrative purposes
specifications motorola mc9328mx1 advance information 39 figure 21. wsc = 1, wws = 2, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs2 r/w lba oe weim_hrdata eb data hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) write last valid data internal signals - shown only for illustrative purposes
40 mc9328mx1 advance information motorola specifications figure 22. wsc = 2, wws = 2, wea = 1, wen = 2, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs2 r/w lba oe data weim_hrdata read nonseq v1 address v1 write data address v8 last valid addr last valid data read write nonseq v8 last valid data read data write read data last valid data write data hwdata data ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
specifications motorola mc9328mx1 advance information 41 figure 23. wsc = 2, wws = 1, wea = 1, wen = 2, edc = 1, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs 2 r/w lba oe data weim_hrdata read nonseq v1 address v1 address v8 last valid addr read data last valid data read write nonseq v8 data hwdata last valid data write data read data write last valid data write data read write idle ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
42 mc9328mx1 advance information motorola specifications figure 24. wsc = 2, csa = 1, wws = 1, a.word/e.half write nonseq v1 address v1 address v1 + 2 last valid addr last valid data write data (word) write last valid data write data (1/2 half word) write data (2/2 half word) hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk addr cs r/w lba oe weim_hrdata eb data hwdata last valid data internal signals - shown only for illustrative purposes
specifications motorola mc9328mx1 advance information 43 figure 25. wsc = 3, csa = 1, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk addr cs 4 r/w l ba oe data weim_hrdata read nonseq v1 address v1 address v8 last valid addr last valid data read last valid data read data write data write nonseq v8 write read data write data last valid data data hwdata ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
44 mc9328mx1 advance information motorola specifications figure 26. wsc = 2, oea = 2, cnc = 3, bcm = 1, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk addr cs4 r/w lba oe data weim_hrdata read nonseq v1 address v1 read data (v1) address v2 last valid last valid data read read seq v2 idle read data (v2) cnc read data (v1) read data (v2) ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
specifications motorola mc9328mx1 advance information 45 figure 27. wsc = 2, oea = 2, wea = 1, wen = 2, cnc = 3, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk addr cs4 r/w lba oe data weim_hrdata read nonseq v1 address v1 address v8 last valid addr read data last valid data read data hwdata write nonseq v8 idle last valid data write data read data write cnc last valid data write data ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
46 mc9328mx1 advance information motorola specifications figure 28. wsc = 3, sync = 1, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs2 r/w lba oe data weim_hrdata nonseq nonse read read idle v1 v5 address v1 last valid addr address v5 read v1 word v2 word v5 word v6 word ecb ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
specifications motorola mc9328mx1 advance information 47 figure 29. wsc = 2, sync = 1, dol = [1/0], a.word/e.word hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs2 r/w lba oe data weim_hrdata ecb nonseq seq read idle v1 seq seq read read read v2 v3 v4 last valid data v1 word v2 word v3 word v4 word address v1 last valid addr read v1 word v2 word v3 word v4 word ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
48 mc9328mx1 advance information motorola specifications figure 30. wsc = 2, sync = 1, dol = [1/0], a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs2 r/w lba oe data weim_hrdata ecb address v1 last valid read v1 1/2 v1 2/2 v2 1/2 v2 2/2 address v2 nonseq seq read idle v1 read v2 last valid data v1 word v2 word ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
specifications motorola mc9328mx1 advance information 49 figure 31. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 2, a.word/e.half non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last read v1 1/2 v1 2/2 v2 1/2 v2 2/2 hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs2 r/w lba oe data weim_hrdata ecb ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
50 mc9328mx1 advance information motorola specifications figure 32. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 1, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk addr cs2 r/w lba oe data weim_hrdata ecb non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last read v1 1/2 v1 2/2 v2 1/2 v2 2/2 ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
specifications motorola mc9328mx1 advance information 51 figure 33. sclk to ld timing diagram 3.8.4 non-tft panel timing figure 34. non-tft panel timing table 18. lcdc sclk timing num characteristic 3.0 +/- 0.3v unit minimum maximum 1 sclk to ld valid ? 3 ns table 19. non tft panel timing diagram symbol parameter allowed register minimum value actual value unit t1 hsyn to vsyn de lay 0 hwait2+2 tpix t2 hsyn pulse width 0 hwidth+1 tpix t3 vsyn to sclk ? 0<= t3<=ts ? t4 sclk to hsyn 0 hwait1+1 tpix lsclk ld[15:0] 1 t1 t2 t4 t3 xmax vsyn sclk hsyn ld[15:0] t2 t1 ts
52 mc9328mx1 advance information motorola specifications ? vsyn, hsyn and sclk can be programmed as ac tive high or active low. in the above timing diagram, all these 3 signals are active high. ? ts is the shift clock period. ? ts = tpix * (panel data bus width). ? tpix is the pixel clock period which equals lcdc_clk period * (pcd + 1). ? maximum frequency of lcdc_clk is 48 mhz, which is controlled by peripheral clock divider register. ? maximum frequency of sclk is hclk / 5, otherwise ld output will be wrong.
specifications motorola mc9328mx1 advance information 53 3.9 pen adc specifications the specifications for the pen adc are shown in table 20 through table 22. 3.10 asp touch panel controller the following sections contain the electrical specificatio ns of the asp touch panel controller. the value of parameters and their corre sponding measuring conditio ns are mentioned as well. 3.10.1 electrical specifications test conditions: temperature = 25 o c, qvdd = 1800mv. table 20. pen adc system performance full range resolution 1 1. tested under input = 0~1.8v at 25c 13 bits non-linearity error 1 4 bits accuracy 1 9 bits table 21. pen adc test conditions vp max 1800 mv ip max +7 a vp min gnd ip min 1.5 a vn gnd in 1.5 a sample frequency 12 mhz sample rate 1.2 khz input frequency 100 hz input range 0?1800 mv note: ru1 = ru2 = 200k table 22. pen adc absolute rating ip max +9.5 a ip min -2.5 a in max +9.5 a in min -2.5 a table 23. asp touch panel controller electrical spec parameter minimum type maximum unit offset ? 32768 ? ? offset error ? ? 8199 ?
54 mc9328mx1 advance information motorola specifications note that qvdd should be 1800mv. 3.10.2 gain calculations the ideal mapping of input voltage to output digital sample is defined as follows: figure 35. gain calculations in general, the mapping function is: s = g * v + c where v is input, s is output, g is the slope, and c is the y-intercept. nominal gain g 0 = 65535 / 4800 = 13.65mv -1 nominal offset c 0 = 65535 / 2 = 32767 gain ? 13.65 ? mv -1 gain error ? ? 33% ? dnl 89?bits inl ?0?bits accuracy (without missing code) 89?bits operating voltage range (pen) ??qvddmv operating voltage range (u) negative qvdd ?qvddmv on-resistance of switches sw[8:1] ?10?ohm table 23. asp touch panel controller electrical spec (continued) parameter minimum type maximum unit 2400 1800 smax 65535 c0 g0 sample vi -2400
specifications motorola mc9328mx1 advance information 55 3.10.3 offset calculations the ideal mapping of input voltage to output digital sample is defined as: figure 36. offset calculations in general, the mapping function is: s = g * v + c where v is input, s is output, g is the slope, and c is the y-intercept. nominal gain g 0 = 65535 / 4800 = 13.65mv -1 nominal offset c 0 = 65535 / 2 = 32767 3.10.4 gain error calculations gain error calculations are made us ing the information in this section. figure 37. gain error calculations assuming the offset remains unchan ged, the mapping is rotated arou nd y-intercept to determine the maximum gain allowed. this occurs when the sample at 1800mv has just reached the ceilin g of the 16-bit range, 65535. 2400 1800 smax 65535 c0 g0 sample vi -2400 2400 1800 smax 65535 c0 g0 sample vi - 2400 gmax
56 mc9328mx1 advance information motorola specifications maximum offset g max, g max = (65535 - c 0) / 1800 = (65535 - 32767) / 1800 = 18.20 gain error g r, g r = (g max - g 0 ) / g 0 * 100% = (18.20 - 13.65) / 13.65 * 100% = 33% 3.11 bluet ooth accelerator the bluetooth accelerator (bta) radio interface su pports the motorola radio, mc13180 using an spi interface. this section provides the data bus timing diagrams and spi in terface timing diagrams shown in figure 38 and figure 39 on page 57, and the associated parameters shown in table 24 and table 25 on page 57. figure 38. motorola mc13 180 data bus timing diagram table 24. motorola mc13180 data bus timing parameter table ref no. parameter minimum typical maximum unit 1 framesync setup time relati ve to bt clk rising edge 1 ?4 ?ns 2 framesync hold time relative to bt clk rising edge 1 ?12 ?ns 3 receive data setup time relative to bt clk rising edge 1 ?6 ?ns 4 receive data hold time rela tive to bt clk rising edge 1 ?13 ?ns 5 transmit data setup time rela tive to rxtx_en rising edge 2 172.5 ? 192.5 s bt clk (bt1) fs (bt5) pkt data (bt3) rxtx_en (bt9) pkt data (bt2) 5 4 3 receive transmit 6 7 8 1 2
specifications motorola mc9328mx1 advance information 57 figure 39. spi interface timing diagram using motorola mc13180 6 tx data period 1000 +/- 0.02 ns 7 bt clk duty cycle 40 ? 60 % 8 transmit data hold time relative to rxtx_en falling edge 4 ? 10 s 1. please refer to motorola 2.4 ghz rf transceiv er module (mc13180) technical data documentation. 2. the setup and hold times of rx_tx_en can be adjusted by programming time_a_b register (0x00216050) and rf_status (0x0021605c) registers. table 25. spi interface timing pa rameter table using motorola mc13180 ref no. parameter minimum maximum unit 1 spi_en setup time relative to rising edge of spi_clk 15 ? ns 2 transmit data delay time relative to rising edge of spi_clk 0 15 ns 3 transmit data hold time relative to rising edge of spi_en 0 15 ns 4 spi_clk rise time 0 25 ns 5 spi_clk fall time 0 25 ns 6 spi_en hold time relative to falling edge of spi_clk 15 ? ns 7 receive data setup time relative to falling edge of spi_clk 1 1. the spi_clk clock frequency and duty cycle, setup and hold times of receive data can be set by programming spi_control (0x00216138) register together with system clock. 15 ? ns 8 receive data hold time relative to falling edge of spi_clk 1 15 ? ns 9 spi_clk frequency, 50% duty cycle required 1 ?20mhz table 24. motorola mc13180 data bus timing parameter table (continued) ref no. parameter minimum typical maximum unit spi_en (bt11) spi_data_out (bt12) spi clk (bt13) spi_data_in (bt4) 1 7 4 5 8 2 3 6 9
58 mc9328mx1 advance information motorola specifications 3.12 spi timing diagrams to use the internal transmit (tx) and receive (rx) data fifos when the spi 1 module is configured as a master, two control signals are used fo r data transfer rate control: the ss signal (output) and the spi_rdy signal (input). the spi 1 sample period control register (periodreg1) and the spi 2 sample period control register (periodreg2) can also be programmed to a fixed data transfer rate for either spi 1 or spi 2. when the spi 1 module is configured as a slav e, the user can configure the spi 1 control register (controlreg1) to match the external spi ma ster?s timing. in this configuration, ss becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data fifo. . figure 40. master spi timing diagram using spi_rdy edge trigger figure 41. master spi timing diagram using spi_rdy level trigger figure 42. master spi timing diagram ignore spi_rdy level trigger figure 43. slave spi timing diag ram fifo advanced by bit count 1 2 3 5 4 ss spirdy sclk, mosi, miso ss spirdy sclk, mosi, miso sclk, mosi, miso ss (output) ss (input) sclk, mosi, miso
specifications motorola mc9328mx1 advance information 59 figure 44. slave spi timing diagram fifo advanced by ss rising edge 3.13 lcd controller this section includes tim ing diagrams for the lcd controller. fo r detailed timing diagrams of the lcd controller with various display configurations , refer to the lcd controller chapter of the mc9328mx1 reference manual . figure 45. sclk to ld timing diagram table 26. timing parameter table for figure 40 through figure 44 ref no. parameter minimum maximum unit 1 spi_rdy to ss output low 2t 1 1. t = cspi system clock period (perclk2). ?ns 2ss output low to first sclk edge 3tsclk 2 2. tsclk = period of sclk. ?ns 3 last sclk edge to ss output high 2tsclk ? ns 4ss output high to spi_rdy low 0 ? ns 5ss output pulse width tsclk + wait 3 3. wait = number of bit clocks (sclk) or 32.768 khz clocks per sample period control register. ?ns 6ss input low to first sclk edge t ? ns 7ss input pulse width t ? ns table 27. lcdc sclk timing parameter table ref no. parameter minimum maximum unit 1 sclk to ld valid ? 2 ns 6 7 ss (input) sclk, mosi, miso 1 lsclk ld[15:0]
60 mc9328mx1 advance information motorola specifications figure 46. 4/8/16 bit/pixel tft color mode panel timing diagram table 28. 4/8/16 bit/pixel tft color mode panel timing table symbol description minimum corresponding register value unit t1 end of oe to b eginning of vsyn t5+t6 +t7+t9 (vwait1t2)+t5+t6+t7+t9 ts t2 hsyn period xmax+5 xma x+t5+t6+t7+t9+t10 ts t3 vsyn pulse widt h t2 vwidth(t2) ts t4 end of vsyn to beginning of oe 2 vwait2(t2) ts t5 hsyn pulse width 1 hwidth+1 ts t6 end of hsyn to beginning to t9 1 hwait2+1 ts t7 end of oe to beginning of hsyn 1 hwait1+1 ts t8 sclk to valid ld data -3 3 ns t9 end of hsyn idle2 to vsyn edge (for non-display region) 22ts t9 end of hsyn idle2 to vsyn edge (for display region) 11ts line 1 line y t1 t4 t3 (1,1) (1,2) (1,x) t5 t7 t6 xmax vsyn hsyn oe ld[15:0] sclk hsyn oe ld[15:0] t2 t8 vsyn display region non-display region line y
specifications motorola mc9328mx1 advance information 61 3.14 multimedia card/secure digital host controller the dma interface block controls all data routing be tween the external data bus (dma access), internal mmc/sd module data bus, and internal system fifo access through a dedicated state machine that monitors the status of fifo content (empty or full) , fifo address, and byte/block counters for the mmc/ sd module (inner system) and th e application (user programming). figure 47. chip-select read cycle timing diagram t10 vsyn to oe active (sharp = 0), when vwait2 = 0 11ts t10 vsyn to oe active (sharp = 1), when vwait2 = 0 22ts note: ? ts is the sclk period which equals lcdc_clk / (pcd + 1). normally lcdc_clk = 15ns. ? vsyn, hsyn and oe can be programmed as active high or active low. in figure 46, all 3 signals are active low. ? the polarity of sclk and ld[15:0] can also be programmed. ? sclk can be programmed to be deactivated during the vsyn pu lse or the oe deasserted period. in figure 46, sclk is always active. ? for t9 non-display region, vsyn is non-active. it is used as an reference. ? xmax is defined in pixels. table 29. sdhc bus timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit min max min max 1 clk frequency at data transfer mode (pp) 1 ? 10/30 cards 0 25/5 0 25/5 mhz 2 clk frequency at identification mode 2 0 400 0 400 khz 3a clock high time 1 ? 10/30 cards 6/33 ? 10/50 ? ns table 28. 4/8/16 bit/pixel tft color mode panel timing table (continued) symbol description minimum corresponding register value unit bus clock 5b 6b 6a 7 5a 4a 3a cmd_dat input cmd_dat output 4b 3b valid data valid data valid data valid data 1 2
62 mc9328mx1 advance information motorola specifications 3.14.1 command respon se timing on mmc/sd bus the card identification and card op eration conditions timing are processe d in open-drain mode. the card response to the host comm and starts after exactly n id clock cycles. for the card address assignment, set_rca is also processed in th e open-drain mode. the minimum dela y between the host command and card response is ncr clock cycles as illustrated in fi gure 48. the symbols for fi gure 48 through figure 52 are defined in table 30. 3b clock low time 1 ? 10/30 cards 15/75 ? 10/50 ? ns 4a clock fall time 1 ? 10/30 cards ? 10/50 (5.00) 3 ? 10/50 ns 4b clock rise time 1 ? 10/30 cards ? 14/67 (6.67) 3 ? 10/50 ns 5a input hold time 3 ? 10/30 cards 5.7/5.7 ? 5/5 ? ns 5b input setup time 3 ? 10/30 cards 5.7/5.7 ? 5/5 ? ns 6a output hold time 3 ? 10/30 cards 5.7/5.7 ? 5/5 ? ns 6b output setup time 3 ? 10/30 cards 5.7/5.7 ? 5/5 ? ns 7 output delay time 3 0 16 0 14 ns 1. c l 100 pf / 250 pf (10/30 cards) 2. c l 250 pf (21 cards) 3. c l 25 pf (1 card) table 30. state signal parameters for figure 48 through figure 52 card active host active symbol definition symbol definition z high impedance state s start bit (0) d data bits t transmitter bit (host = 1, card = 0) * repetition p one-cycle pull-up (1) crc cyclic redundancy check bits (7 bits) e end bit (1) table 29. sdhc bus timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit min max min max
specifications motorola mc9328mx1 advance information 63 figure 48. timing diagra ms at identification mode after a card receives its rca, it switches to data transf er mode. as shown on the first diagram in figure 49 on page 63, sd_cmd lines in this mo de are driven with push-pull driv ers. the command is followed by a period of two z bits (allowing time for direction switching on the bus) and then by p bits pushed up by the responding card. the other two diagrams show the separating periods n rc and n cc . figure 49. timing diagrams at data transfer mode figure 50 on page 64 shows basic read operation timing. in a read operation, the sequence starts with a single block read command (which specifies the start ad dress in the argument field). the response is sent on the sd_cmd lines as usual. data transmission from the card starts after the access time delay n ac , beginning from the last bit of the read command. if the sy stem is in multiple block read mode, the card sends a continuous flow of data blocks with distance n ac until the card sees a stop transmission command. the data stops two clock cycles after the end bit of the stop command. set_rca timing identification timing host command cid/ocr n id cycles cmd content s t e z z s t content z z ****** crc z host command cid/ocr n cr cycles cmd content s t e z z s t content z z ****** crc z timing of command sequences (all modes) timing response end to next cmd start (data transfer mode) command response timing (data transfer mode) host command response n cr cycles cmd content s t e z z p p s t content crc e z z ****** crc z response host command n rc cycles cmd content s t e z z s t content crc e z z ****** crc z host command host command n cc cycles cmd content s t e z z s t content crc e z z ****** crc z
64 mc9328mx1 advance information motorola specifications figure 50. timing diagrams at data read figure 51 on page 65 shows the basic write operation ti ming. as with the read op eration, after the card response, the data transfer starts after n wr cycles. the data is suffixed with crc ch eck bits to allow the card to check for transmission errors. the card sends back the crc check result as a cc status token on the data line. if there was a transmission error, th e card sends a negative crc st atus (101); otherwise, a positive crc status (010) is returned. the card expects a continuous flow of data bl ocks if it is configured to multiple block mode, with the flow terminated by a stop transmission command. n ac cycles read data timing of single block read n ac cycles read data timing of multiple block read n ac cycles n st timing of stop command (cmd12, data transfer mode) host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc dat z****z z z p p s d ***** d d d dat z****z z z p p s d ***** ****** d d d p ***** p s d d d d ****** host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc ***** read data host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc valid read data dat ***** z z e ***** d d d d d d d d z
specifications motorola mc9328mx1 advance information 65 figure 51. timing diagrams at data write write data busy write data write data host command response n cr cycles cmd dat timing of the block write command n wr cycles busy crc status cmd dat timing of the multiple block write command content crc status n wr cycles crc status e z z p p p p ****** z z p p s crc e z z s e z p p s content crc e z z s e s e z x x x x x x l*l x x x x x x status status dat content z z p p s crc e z z x x z p p s content crc e z z x x x x x x x x x x z n wr cycles x x x x x x z****z z z z p p s content crc e z z s e s e z l*l status x x x x x x x z x x x e z z p p s content crc z z z dat z****z content s t crc e z z p p s t content crc e z z p ****** ****** p p p
66 mc9328mx1 advance information motorola specifications the stop transmission command may occur when the ca rd is in different states. figure 52 shows the different scenarios on the bus. figure 52. stop transmission during different scenarios write data stop transmission during data transfer from the host. busy (card is programming) stop transmission during crc status transfer from the card. stop transmission received after last data block. card becomes busy programming. stop transmission received after last data block. card becomes busy programming. host command card response n cr cycles cmd content s t e z z p p s t content crc e z z ****** host command content s t crc e dat ****** d d d d d d z z z z d d d d d d d e z z s l z z z z z z z z z z z z z z z z z z z z z z e dat ****** d d d d d d z z z z d z z s z z s l z z z z z z z z z z z z z z z z z z z z z z e crc e crc dat ****** s l z z z z z z z z z z z z z z z z z z z z z z z z z z e dat ****** z z z z z z z z z z z z z z z z z z z z s l z z z z z z z z z z z z z z z z z z z z z z e z
specifications motorola mc9328mx1 advance information 67 3.14.2 sdio-irq and re adwait service handling in sdio, there is a 1-bit or 4-bit interrupt respon se from the sdio peripheral card. in 1-bit mode, the interrupt response is simply that th e sd_dat[1] line is held low. the sd _dat[1] line is not used as data in this mode. the memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed (s d_dat[1] returns to its high level). in 4-bit mode, the interrupt is less simple. the interrupt triggers at a pa rticular period called the "interrupt period" during the data access, and the controller must sample sd_dat[1] during this short period to determine the irq status of the attached card. the in terrupt period only happens at the boundary of each block (512 bytes). figure 53. sdio irq timing diagram readwait is another feature in sdio that allows the us er to submit commands during the data transfer. in this mode, the block temporarily pauses the data transf er operation counter and related status, yet keeps the clock running, and allows the user to submit commands as normal. afte r all commands are submitted, the user can switch back to the data transfer operation and all counter and status values are resumed as access continues. table 31. timing values for figure 48 through figure 52 parameter symbol minimum maximum unit mmc/sd bus clock, clk (all values are re ferred to minimum (vih) and maximum (vil) command response cycle ncr 2 64 clock cycles identification response cycle nid 5 5 clock cycles access time delay cycle nac 2 taac + nsac clock cycles command read cycle nrc 8 ? clock cycles command-command cycle ncc 8 ? clock cycles command write cycle nwr 2 ? clock cycles stop transmission cycle nst 2 2 clock cycles taac: data read access time -1 defined in csd register bit[119:112] nsac: data read access time -2 in clk cycles (nsac100) defined in csd register bit[111:104] interrupt period irq irq dat[1] for 4-bit l h interrupt period dat[1] for 1-bit cmd content s t e z z p e z z ****** z z response crc s z z e s block data e s block data
68 mc9328mx1 advance information motorola specifications figure 54. sdio readwait timing diagram 3.15 memory stick host controller the memory stick protocol requires three interface signal line connec tions for data transfers: ms_bs, ms_sdio, and ms_sclko. communication is always initiated by the mshc and operates the bus in either four-state or two-state access mode. the ms_bs signal classifies data on the sdio into one of four states (bs0, bs1, bs2, or bs3) according to its attribute and transfer direction. bs0 is the in t transfer state, and duri ng this state no packet transmissions occur. during the bs1, bs2, and bs3 states, packet comm unications are executed. the bs1, bs2, and bs3 states are regarded as one packet le ngth and one communicatio n transfer is always completed within one packet length (in fo ur-state access mode). the memory stick usually operates in four state acces s mode and in bs1, bs2, and bs3 bus states. when an error occurs during packet communication, the mode is shifted to two-state access mode, and the bs0 and bs1 bus states are automatically repeat ed to avoid a bus collision on the sdio. dat[1] for 4-bit dat[2] for 4-bit cmd ****** p s t e z z ****** cmd52 z crc e z z s block data l l l l l l l l l l l l l l l l l l l l l h z s e s block data e block data z z l h e s block data
specifications motorola mc9328mx1 advance information 69 figure 55. mshc si gnal timing diagram table 32. mshc signal timing parameter table ref no. parameter minimum maximum unit 1 ms_sclki frequency ? 25 mhz 2 ms_sclki high pulse width 20 ? ns 3 ms_sclki low pulse width 20 ? ns 4 ms_sclki rise time ? 3 ns 5 ms_sclki fall time ? 3 ns 6 ms_sclko frequency 1 ?25mhz 7 ms_sclko high pulse width 1 20 ? ns 8 ms_sclko low pulse width 1 15 ? ns 9 ms_sclko rise time 1 ?5ns 10 ms_sclko fall time 1 ?5ns 11 ms_bs delay time 1 ?3ns ms_sclko 11 ms_bs ms_sdio (output) ms_sdio (input) ms_sdio (input) 11 12 12 13 14 15 16 (red bit = 0) (red bit = 1) ms_sclki 1 6 2 3 7 8 4 5 9 10
70 mc9328mx1 advance information motorola specifications 3.16 pulse-width modulator the pwm can be programmed to select one of two cl ock signals as its source frequency. the selected clock signal is passed through a divider and a prescaler before being input to th e counter. the output is available at the pulse-width modula tor output (pwmo) external pin. figure 56. pwm output timing diagram 12 ms_sdio output delay time 1,2 ?3ns 13 ms_sdio input setup time for ms_sclko rising edge (red bit = 0) 3 18 ? ns 14 ms_sdio input hold time for ms_sclko rising edge (red bit = 0) 3 0?ns 15 ms_sdio input setup time for ms_sclko falling edge (red bit = 1) 4 23 ? ns 16 ms_sdio input hold time for ms_sclko falling edge (red bit = 1) 4 0?ns 1. loading capacitor condition is less than or equal to 30pf. 2. an external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the ms_sdio pin, because of a possibility of signal conflict between the ms_sdio pin and memory stick sdio pin when the pin direction changes. 3. if the msc2[red] bit = 0, mshc samples ms _sdio input data at ms_sclko rising edge. 4. if the msc2[red] bit = 1, mshc samples ms_sdio input data at ms_sclko falling edge. table 33. pwm output timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum m inimum maximum 1 system clk frequency 1 0870100mhz 2a clock high time 1 3.3 ? 5/10 ? ns 2b clock low time 1 7.5 ? 5/10 ? ns 3a clock fall time 1 ?5?5/10ns 3b clock rise time 1 ?6.67?5/10ns table 32. mshc signal timing parameter table (continued) ref no. parameter minimum maximum unit system clock 2a 1 pwm output 3b 2b 3a 4b 4a
specifications motorola mc9328mx1 advance information 71 3.17 sdram memory controller a write to an address within the memory region in itiates the program sequence. the first command issued to the syncflash is load comman d register. a [7:0] determine whic h operation the command performs. for this write setup operation, an address of 0x40 is hardware generated. the bank and other address lines are driven with the address to be programmed. th e next command is active which registers the row address and confirms the bank address. the third command supplies the column address, re-confirms the bank address, and supplies the data to be written. syncflash does not support burst writes, therefore a burst terminate comman d is not required. a read to the memory region initiates the status read sequence. the first comman d issued to the syncflash is the load command register with a [7:0] set to 0x70 which correspon ds to the read status register operation. the bank and other address lines are driv en to the selected address . the second command is active which sets up the status register read. the ba nk and row addresses are driven during this command. the third command of the triplet is read. bank and column addresses ar e driven on the address bus during this command. data is re turned from memory on the low order 8 data bits following the cas latency. 4a output delay time 1 5.7 ? 5 ? ns 4b output setup time 1 5.7 ? 5 ? ns 1. c l of pwmo = 30 pf table 33. pwm output timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum m inimum maximum
72 mc9328mx1 advance information motorola specifications figure 57. sdram/syncflas h read cycle timing diagram table 34. sdram ti ming parameter table ref no. parameter 1.8v 3.3v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns 3 sdram clock cycle time 10.4 ? 10 ? ns 3s cs, ras, cas, we, dqm setup time 3.42 ? 3 ? ns 3h cs, ras, cas, we, dqm hold time 2.28 ? 2 ? ns 4s address setup time 3.42 ? 3 ? ns sdclk we addr dq dqm row/ba col/ba 3s 3h 3s 3h 3s 3 s 3h 3h 3h 4s 4h 5 3s 3 2 1 8 data 7 6 cs cas ras note: cke is high during the read/write cycle.
specifications motorola mc9328mx1 advance information 73 4h address hold time 2.28 ? 2 ? ns 5 sdram access time (cl = 3) ? 6.84 ? 6 ns 5 sdram access time (cl = 2) ? 6.84 ? 6 ns 5 sdram access time (cl = 1) ? 22 ? 22 ns 6 data out hold time 2.85 ? 2.5 ? ns 7 data out high-impedance time (cl = 3) ? 6.84 ? 6 ns 7 data out high-impedance time (cl = 2) ? 6.84 ? 6 ns 7 data out high-impedance time (cl = 1) ? 22 ? 22 ns 8 active to read/write command period (rc = 1) t rcd 1 ? t rcd 1 ?ns 1. t rcd = sdram clock cycle time. the t rcd setting can be found in the mc9328mx1 reference manual. table 34. sdram timing parameter table (continued) ref no. parameter 1.8v 3.3v unit minimum maximum minimum maximum
74 mc9328mx1 advance information motorola specifications figure 58. sdram/syncflash write cycle timing diagram table 35. sdram write timing parameter table ref no. parameter 1.8v 3.3v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns 3 sdram clock cycle time 10.4 ? 10 ? ns 4 address setup time 3.42 ? 3 ? ns 5 address hold time 2.28 ? 2 ? ns 6 precharge cycle period 1 t rp 2 ? t rp 2 ?ns 7 active to read/write command delay t rcd 2 ? t rcd 2 ?ns 8 data setup time 4.0 ? 2 ? ns sdclk cs cas we ras addr dq dqm / ba row/ba 3 4 6 1 col/ba data 2 5 7 8 9
specifications motorola mc9328mx1 advance information 75 figure 59. sdram refresh timing diagram 9 data hold time 2.28 ? 2 ? ns 1. precharge cycle timing is incl uded in the write timing diagram. 2. t rp and t rcd = sdram clock cycle time. these settings can be found in the mc9328mx1 reference manual. table 36. sdram refresh timing parameter table ref no. parameter 1.8v 3.3v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns 3 sdram clock cycle time 10.4 ? 10 ? ns table 35. sdram write timing parameter table (continued) ref no. parameter 1.8v 3.3v unit minimum maximum minimum maximum sdclk cs cas we ras addr dq dqm ba 3 4 6 1 2 5 7 row/ba 7
76 mc9328mx1 advance information motorola specifications figure 60. sdram self-refresh cycle timing diagram 4 address setup time 3.42 ? 3 ? ns 5 address hold time 2.28 ? 2 ? ns 6 precharge cycle period t rp 1 ? t rp 1 ?ns 7 auto precharge command period t rc 1 ? t rc 1 ?ns 1. t rp and t rc = sdram clock cycle time. these settings can be found in the mc9328mx1 reference manual. table 36. sdram refresh timi ng parameter table (continued) ref no. parameter 1.8v 3.3v unit minimum maximum minimum maximum sdclk cs cas ras addr dq dqm ba we cke
specifications motorola mc9328mx1 advance information 77 3.18 usb device port four types of data transfer modes exist for the usb mo dule: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. from the perspectiv e of the usb module, the interrupt transfer type is identical to the bulk data transfer mode, and no additional ha rdware is supplied to su pport it. this section covers the transfer modes and ho w they work from the ground up. data moves across the usb in packets. groups of p ackets are combined to form data transfers. the same packet transfer mechanism applies to bulk, interrupt, an d control transfers. isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the usb bandwidth at all times, there is no end-of-transfer. figure 61. usb device timing diagram for data transfer to usb transceiver (tx) table 37. usb device timing parameter table for data transfer to usb transceiver (tx) ref no. parameter minimum maximum unit 1t roe_vpo ; usbd_roe active to usbd_vpo low 83.14 83.47 ns 2t roe_vmo ; usbd_roe active to usbd_vmo high 81.55 81.98 ns 3t vpo_roe ; usbd_vpo high to usbd_roe deactivated 83.54 83.80 ns 4t vmo_roe ; usbd_vmo low to usbd_roe deactivated (includes se0) 248.90 249.13 ns 5t feopt ; se0 interval of eop 160.00 175.00 ns 6t period ; data transfer rate 11.97 12.03 mb/s usbd_afe (output) usbd_roe (output) usbd_vpo (output) usbd_vmo (output) usbd_suspnd (output) usbd_rcv (input) usbd_vp (input) usbd_vm (input) t roe_vpo t vmo_roe t vpo_roe t feopt t roe_vmo t period 1 2 3 4 5 6
78 mc9328mx1 advance information motorola specifications figure 62. usb device timing diagram for data transfer from usb transceiver (rx) table 38. usb device timing parameter table for data transfer from usb transceiver (rx) ref no. parameter minimum maximum unit 1t feopr ; receiver se0 interval of eop 82 ? ns usbd_afe (output) usbd_roe (output) usbd_vpo (output) usbd_vmo (output) (output) usbd_suspnd (input) usbd_vp usbd_rcv (input) usbd_vm (input) t feopr 1
specifications motorola mc9328mx1 advance information 79 3.19 i 2 c module the i 2 c communication protocol consists of seven elements: start, data source/recipient, data direction, slave acknowledge, da ta, data acknowledge, and stop. figure 63. definition of bus timing for i 2 c 3.20 synchronous serial interface the mc9328mx1 processor contains two identical ssi modules. the transmit and receive sections of the ssi can be synchronous or asynch ronous. in synchronous mode, the transmitter and the receiver use a common clock and frame sy nchronization signal. in asynchronous mode, the transmitte r and receiver each have their own clock and frame synchronization signals. continuous or gated clock mode can be selected. in continuous mode, the clock runs continuously. in gated clock mode, the clock functions only during transmission. the internal and exte rnal clock timing diagrams are shown in figure 65 through figure 67 on page 81. normal or network mode can also be selected. in no rmal mode, the ssi functions with one data word of i/o per frame. in network mode, a frame can contain between 2 and 32 data words. network mode is typically used in star or ring-tim e division multiplex networ ks with other processors or codecs, allowing interface to time division multiplexed networks withou t additional logic. use of the gated clock is not allowed in network mode. these dist inctions result in the basic opera ting modes that allow the ssi to communicate with a wide variety of devices. table 39. i 2 c bus timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum 1 hold time (repeated) start condition 182 ? 160 ? ns 2 data hold time 01710150ns 3 data setup time 11.4 ? 10 ? ns 4 high period of the scl clock 80 ? 120 ? ns 5 low period of the scl clock 480 ? 320 ? ns 6 setup time for stop condition 182.4 ? 160 ? ns sda scl 1 2 3 4 6 5
80 mc9328mx1 advance information motorola specifications note: srxd input in synchronous mode only. figure 64. ssi transmitter internal clock timing diagram figure 65. ssi receiver internal clock timing diagram stck output stfs (bl) output stfs (wl) output 1 2 6 8 10 11 stxd output srxd input 32 31 4 12 srck output srfs (bl) output srfs (wl) output 3 7 srxd input 13 14 1 5 9
specifications motorola mc9328mx1 advance information 81 figure 66. ssi transmitter external clock timing diagram figure 67. ssi receiver ex ternal clock timing diagram table 40. ssi 1 timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum m inimum maximum internal clock operation 1 (port c primary function) 2 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.5 4.5 1.3 3.9 ns 3 srck high to srfs (bl) high 3 -1.2 -1.7 -1.1 -1.5 ns stck input 16 stfs (bl) input stfs (wl) input 17 18 22 24 26 stxd output srxd input 27 28 34 note: srxd input in synchronous mode only. 33 20 15 srck input 16 srfs (bl) input srfs (wl) input 17 19 23 srxd input 29 30 21 25 15
82 mc9328mx1 advance information motorola specifications 4 stck high to stfs (bl) low 3 2.5 4.3 2.2 3.8 ns 5 srck high to srfs (bl) low 3 0.1 -0.8 0.1 -0.8 ns 6 stck high to stfs (wl) high 3 1.48 4.45 1.3 3.9 ns 7 srck high to srfs (wl) high 3 -1.1 -1.5 -1.1 -1.5 ns 8 stck high to stfs (wl) low 3 2.51 4.33 2.2 3.8 ns 9 srck high to srfs (wl) low 3 0.1 -0.8 0.1 -0.8 ns 10 stck high to stxd valid from high impedance 14.25 15.73 12.5 13.8 ns 11a stck high to stxd high 0.91 3.08 0.8 2.7 ns 11b stck high to stxd low 0.57 3.19 0.5 2.8 ns 12 stck high to stxd high impedance 12.88 13.57 11.3 11.9 ns 13 srxd setup time before srck low 21.1 ? 18.5 ? ns 14 srxd hold time after srck low 0 ? 0 ? ns external clock op eration (port c primary function) 2 15 stck/srck clock period 1 92.8 ? 81.4 ? ns 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns 18 stck high to stfs (bl) high 3 ? 92.8 0 81.4 ns 19 srck high to srfs (bl) high 3 ? 92.8 0 81.4 ns 20 stck high to stfs (bl) low 3 ? 92.8 0 81.4 ns 21 srck high to srfs (bl) low 3 ? 92.8 0 81.4 ns 22 stck high to stfs (wl) high 3 ? 92.8 0 81.4 ns 23 srck high to srfs (wl) high 3 ? 92.8 0 81.4 ns 24 stck high to stfs (wl) low 3 ? 92.8 0 81.4 ns 25 srck high to srfs (wl) low 3 ? 92.8 0 81.4 ns 26 stck high to stxd valid from high impedance 18.01 28.16 15.8 24.7 ns 27a stck high to stxd high 8.98 18.13 7.0 15.9 ns 27b stck high to stxd low 9.12 18.24 8.0 16.0 ns table 40. ssi 1 timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum m inimum maximum
specifications motorola mc9328mx1 advance information 83 28 stck high to stxd high impedance 18.47 28.5 16.2 25.0 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30 srxd hole time after srck low 0 ? 0 ? ns synchronous internal clock oper ation (port c primary function) 2 31 srxd setup before stck falling 15.4 ? 13.5 ? ns 32 srxd hold after stck falling 0 ? 0 ? ns synchronous external clock oper ation (port c primary function) 2 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34 srxd hold after stck falling 0 ? 0 ? ns 1. all the timings for the ssi are given for a non-inve rted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the pol arity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. 2. there are 2 sets of i/o signals for the ssi module. they are from port c primary function (pc3 ? pc8) and port b alternate function (pb14 ? pb19). when ssi signals are configured as outputs, they can be viewed both at port c primary function and port b alternate function. when ssi signals are configured as input, the ssi module selects the input based on status of the fmcr register bits in the clock controller module (crm). by default, the input are selected from port c primary function. 3. bl = bit length; wl = word length. table 41. ssi 2 timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum internal clock operation 1 (port b alternate function) 2 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.7 4.8 1.5 4.2 ns 3 srck high to srfs (bl) high 3 -0.1 1.0 -0.1 1.0 ns 4 stck high to stfs (bl) low 3 3.08 5.24 2.7 4.6 ns 5 srck high to srfs (bl) low 3 1.25 2.28 1.1 2.0 ns 6 stck high to stfs (wl) high 3 1.71 4.79 1.5 4.2 ns 7 srck high to srfs (wl) high 3 -0.1 1.0 -0.1 1.0 ns 8 stck high to stfs (wl) low 3 3.08 5.24 2.7 4.6 ns table 40. ssi 1 timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum m inimum maximum
84 mc9328mx1 advance information motorola specifications 9 srck high to srfs (wl) low 3 1.25 2.28 1.1 2.0 ns 10 stck high to stxd valid from high impedance 14.93 16.19 13.1 14.2 ns 11a stck high to stxd high 1.25 3.42 1.1 3.0 ns 11b stck high to stxd low 2.51 3.99 2.2 3.5 ns 12 stck high to stxd high impedance 12.43 14.59 10.9 12.8 ns 13 srxd setup time before srck low 20 ? 17.5 ? ns 14 srxd hold time after srck low 0 ? 0 ? ns external clock operation (port b alternate function) 2 15 stck/srck clock period 1 92.8?81.4?ns 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns 18 stck high to stfs (bl) high 3 ?92.8081.4ns 19 srck high to srfs (bl) high 3 ?92.8081.4ns 20 stck high to stfs (bl) low 3 ?92.8081.4ns 21 srck high to srfs (bl) low 3 ?92.8081.4ns 22 stck high to stfs (wl) high 3 ?92.8081.4ns 23 srck high to srfs (wl) high 3 ?92.8081.4ns 24 stck high to stfs (wl) low 3 ?92.8081.4ns 25 srck high to srfs (wl) low 3 ?92.8081.4ns 26 stck high to stxd valid from high impedance 18.9 29.07 16.6 25.5 ns 27a stck high to stxd high 9.23 20.75 8.1 18.2 ns 27b stck high to stxd low 10.60 21.32 9.3 18.7 ns 28 stck high to stxd high impedance 17.90 29.75 15.7 26.1 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30 srxd hole time after srck low 0 ? 0 ? ns table 41. ssi 2 timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum
motorola mc9328mx1 advance information 85 notes synchronous internal clock operation (port b alternate function) 2 31 srxd setup before stck falling 18.81 ? 16.5 ? ns 32 srxd hold after stck falling 0 ? 0 ? ns synchronous external clock operation (port b alternate function) 2 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34 srxd hold after stck falling 0 ? 0 ? ns 1. all the timings for both ssi modules are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by invert ing the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. 2. there is one set of i/o signals for the ssi2 module. they are from port c alternate function (pc19 ? pc24). when ssi signals are configured as outputs, they can be viewed at port c alternate function a. when ssi signals are configured as inputs, the ssi mo dule selects the input based on fmcr register bits in the clock controller module (crm). by default, t he input is selected from port c alternate function. 3. bl = bit length; wl = word length table 41. ssi 2 timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum
86 mc9328mx1 advance information motorola specifications 3.21 cmos sensor interface the csi module consists of a cont rol register to configure the inte rface timing, a control register for statistic data generation, a status register, interface logic, a 32 32 image data receive fifo, and a 16 32 statistic data fifo. 3.21.1 gated clock mode figure 68 shows the timing diagram when the cmos sensor output data is configured for negative edge and the csi is programmed to received data on th e positive edge. figure 69 on page 87 shows the timing diagram when the cmos sensor output data is config ured for positive edge and the csi is programmed to received data in negative edge. the parameters for the timing diagrams are liste d in table 42 on page 87. figure 68. sensor output data on pixel clock falling edge csi latches data on pixel clock rising edge 1 3 6 5 vsync hsync pixclk data[7:0] valid data valid data valid data 4 7 2
specifications motorola mc9328mx1 advance information 87 figure 69. sensor output data on pixel clock rising edge csi latches data on pixel clock falling edge the limitation on pixel clock rise time / fall time are not specified. it should be calculated from the hold time and setup time, according to: rising-edge latch data max rise time allowed = (positiv e duty cycle - hold time) max fall time allowed = (nega tive duty cycle - setup time) in most of case, duty cycle is 50 / 50, therefore max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) for example: given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns table 42. gated clock mode timing parameters ref no. parameter minimum maximum unit 1 csi_vsync to csi_hsync 9 * t hclk ?ns 2 csi_hsync to csi_pixclk 3 (tp / 2) - 3 ns 3 csi_d setup time 1 ? ns 4 csi_d hold time 1 ? ns 5 csi_pixclk high time 10.42 ? ns 6 csi_pixclk low time 10.42 ? ns 7 csi_pixclk frequency 0 48 mhz 1 3 6 5 vsync hsync pixclk data[7:0] valid data valid data valid data 4 7 2
88 mc9328mx1 advance information motorola specifications negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns falling-edge latch data max fall time allowed = (nega tive duty cycle - hold time) max rise time allowed = (pos itive duty cycle - setup time) 3.21.2 non-gated clock mode figure 70 shows the timing diagram when the cmos sensor output data is configured for negative edge and the csi is programmed to received data on th e positive edge. figure 71 on page 89 shows the timing diagram when the cmos sensor output data is config ured for positive edge and the csi is programmed to received data in negative edge. the parameters for the timing diagrams are liste d in table 43 on page 89. figure 70. sensor output data on pixel clock falling edge csi latches data on pixel clock rising edge 1 vsync pixclk data[7:0] 23 6 4 5 valid data valid data valid data
specifications motorola mc9328mx1 advance information 89 figure 71. sensor output data on pixel clock rising edge csi latches data on pixel clock falling edge the limitation on pixel clock rise time / fall time are not specified. it should be calculated from the hold time and setup time, according to: max rise time allowed = (positiv e duty cycle - hold time) max fall time allowed = (nega tive duty cycle - setup time) in most of case, duty cycle is 50 / 50, therefore: max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) for example: given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns table 43. non-gated clock mode parameters ref no. parameter minimum maximum unit 1 csi_vsync to csi_pixclk 9 * t hclk ?ns 2 csi_d setup time 1 ? ns 3 csi_d hold time 1 ? ns 4 csi_pixclk high time 10.42 ? ns 5 csi_pixclk low time 10.42 ? ns 6 csi_pixclk frequency 0 48 mhz 1 vsync pixclk data[7:0] 2 3 6 5 4 valid data valid data valid data
90 mc9328mx1 advance information motorola specifications falling-edge latch data max fall time allowed = (nega tive duty cycle - hold time) max rise time allowed = (pos itive duty cycle - setup time)
p i n - o u t a n d p a c k a g e i n f o r m a t i o n motorola mc9328mx1 advance information 91 4 pin-out and package information table 44. mc9328mx1 bga pin assignments 12 3 4 5 6 7 8 91011121314 1516 a vs s sd_d at3 sd_c lk vss usbd_ afe nvdd 4 vss uart 1_rt s uart 1_rx d nvdd 3 bt5 bt3 qvdd 4 rvp uip nc b a2 4 sd_d at1 sd_c md sim_t x usbd_ oe usbd _vp ssi_r xclk ssi_t xclk spi1_ sclk bt11 bt7 bt1 vss rvm uin nc c a2 3 d31 sd_d at0 sim_p d usbd_ rcv uart 2_ct s uart 2_rx d ssi_r xfs uart 1_tx d btrf gnd bt8 btrfv dd nc avdd 2 vss r1b d a2 2 d30 d29 sim_s ven usbd_ suspn d usbd _vpo usbd _vmo ssi_r xdat spi1_ spi_r dy bt13 bt6 nc nc nc r1a r2b e a2 0 a21 d28 d26 sd_da t2 usbd _vm uart 2_rt s ssi_t xdat spi1_ ss bt12 bt4 nc nc py2 px2 r2a f a1 8 d27 d25 a19 a16 sim_r st uart 2_tx d ssi_t xfs spi1_ miso bt10 bt2 rev py1 px1 lsclk spl_ spr g a1 5 a17 d24 d23 d21 sim_r x sim_c lk uart 1_ct s spi1_ mosi bt9 cls contr ast acd/ oe lp/ hsyn c flm/ vsync ld1 h a1 3 d22 a14 d20 nvdd1 nvdd 1 vss vss qvdd 1 ps ld0 ld2 ld4 ld5 ld9 ld3 j a1 2 a11 d18 d19 nvdd1 nvdd 1 vss nvdd 1 vss vss ld6 ld7 ld8 ld11 qvdd3 vss k a1 0 d16 a9 d17 nvdd1 vss vss nvdd 1 nvdd 2 nvdd 2 ld10 ld12 ld13 ld14 tmr2o ut ld15
92 mc9328mx1 advance information motorola l a8 a7 d13 d15 d14 nvdd 1 vss cas tck tin pwm o csi_m clk csi_d 0 csi_d 1 csi_d2 csi_d 3 m a5 d12 d11 a6 sdclk vss rw ma10 ras rese t_in big_e ndia n csi_d4 csi_h sync csi_v sync csi_d6 csi_d 5 n a4 eb1 d10 d7 a0 d4 pa17 d1 dqm1 rese t_sf rese t_ou t boot2 csi_p ixclk csi_d 7 tms tdi p a3 d9 eb0 cs3 d6 ecb d2 d3 dqm3 sdck e1 boot 3 boot0 trst i2c_s cl i2c_sd a xtal 32k r eb 2 eb3 a1 cs4 d8 d5 lba bclk d0 dqm0 sdck e0 por boot 1 tdo qvdd2 exta l32k t vs s a2 oe cs5 cs2 cs1 cs0 ma11 dqm2 sdwe clko avdd1 trist ate exta l16m xtal16 m vss table 44. mc9328mx1 bga pin assignments (continued) 12 3 4 5 6 7 8 91011121314 1516
pin-out and package information motorola mc9328mx1 advance information 93 4.1 mapbga package dimensions figure 72 illustrates the mapbga 14 mm 14 mm 1.30 mm package, which has 0.8 mm spacing between the pads. the device design ator for the mapbga package is vh. figure 72. mc9328mx1 mapbga mechanical drawing
mc9328mx1/d how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minat o-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or inte grated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or spec ifications can and do vary in di fferent applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against a ll claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. all other product or service names are the property of their respective owners. the arm powered logo is the registered trademarks of ar m limited. arm9, arm920t, and arm9tdmi are the trademarks of arm limited. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2003

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